`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2020/11/11 11:13:29
// Design Name: 
// Module Name: timer
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module timer(
    input clk_i,  // 100MHz clock input
    input rst_i,  // highpos reset
    output reg [3:0] highdigit_o,
    output reg [3:0] lowdigit_o
    );
    
    wire clk_2hz;
    (* KEEP="TRUE" *) reg [3:0] cnt = 4'b0000;
    divider_2hz DIVIDER(clk_i, 1'b0, clk_2hz);
    
    always @(posedge clk_2hz or posedge rst_i) begin
        if (rst_i==1'b1) begin
            highdigit_o = 4'b1;
            lowdigit_o = 4'b0;
            cnt = 4'b1010;
        end else if (cnt==4'b0000) begin
            highdigit_o = 4'b0;
            lowdigit_o = 4'b0;
            cnt = 4'b1010;
        end else if (cnt==4'b1010) begin
            highdigit_o = 4'b1;
            lowdigit_o = 4'b0;
            cnt = cnt - 4'b1;
        end else begin
            highdigit_o = 4'b0;
            lowdigit_o = cnt;
            cnt = cnt - 4'b1;
        end
    end
endmodule
